Summary
TPA2028D1 is a low-power Class-D amplifier with AGC / DRC function introduced by TI for portable devices. Because of its outstanding performance, it has been widely used in the industry. And it can be configured through I2C itself, so that designers can optimize the chip settings according to different applications to obtain better results.
This article discusses how to optimize the TPA2028D1 settings so that it can better respond quickly to sudden pronunciations in devices such as smartphones, such as keyboard tones and prompt tones.
1 Introduction
TPA2028D1 is a high-efficiency Class-D amplifier launched by TI for mobile devices. The integrated DRC and AGC functions can automatically adjust the gain of the amplifier according to the size of the input signal to achieve the purpose of preventing power amplifier clipping distortion, and effectively increase the average output power, thereby improving music playback.
TPA2028D1 has flexible configurability. Designers can access their registers through I2C, configure multiple parameters such as amplifier enable, gain, and response speed, so that they can be optimized for different application scenarios.
Since DRC and AGC adjust the gain according to the signal size, certain Attack TIme and Release TIme need to be set for continuous music signals to ensure excellent playback effects. However, the duration of the burst sound signal is too short, and due to the need for power saving, the TPA2028D1 needs to be enabled before playback, and turned off after playback. Therefore, in some designs, when playing, for example, keyboard sounds or camera sounds, there is a phenomenon that the sound is too low, or the sound gradually fades.
This paper analyzes the cause of this phenomenon and discusses how to solve similar problems by optimizing the setting of chip parameters.
2. TPA2028 two kinds of shutdown / enable mode
TPA2028 can be turned off and enabled through hardware and software.
l Through the EN pin of the chip, the hardware is turned off;
l Through the chip register 0x01 bit6 EN and bit5 SWS, the software can be turned off
2.1
2.2
2.1 Hardware off / enable
shut down:
l The EN pin is set low, the chip enters the off state, and all registers are cleared
Enable:
l The EN pin is set high, the chip enters the enable state, and all registers enter the initial state, as shown in Table 1. Because in the initial state register 0x01 EN = 1 SWS = 0, the power amplifier is partially enabled and can be played directly;
Table 1. Initial value of TPA2028D1 register
The design of TPA2028D1 is that after the chip is enabled, the initial gain of the amplifier is determined by Fixed Gain. The initial value of Reg5 / bit5: 0 of TPA2028D1 Fixed Gain register is 00110, which is 6dB, so the initial value of the amplifier's gain in this state is fixed at 6dB. Since the initial value of Reg7 / bit7: 4 in the Max Gain register is 30dB, the signal played at this time is gradually increased from 6dB to 30dB at the speed of the initial value of the Reg3 / bit5: 0 in the Release time register, Reg. As shown in Figure 1. Therefore, it will cause a significant fade-in effect, and for signals that are too short-lived, it will cause too small a phenomenon.
Figure 1. Hardware enabled TPA2028D1 gain increment
2.2 Software close / enable
shut down:
l EN = 0 (Reg1 / bit6) or SWS = 1 (Reg1 / bit5)
Enable:
l EN = 1 (Reg1 / bit6) or SWS = 0 (Reg1 / bit5)
EN and SWS will not clear the register setting status, all register values ​​maintain the original settings, so TPA2028D1 can be changed according to the set Fixed Gain and Max Gain and Release Time after the software is enabled. As shown in Figure 2. Therefore, you only need to set the appropriate Fixed Gain, Max Gain, and Release Time to control this change, thereby eliminating the fade-in and fade-out problems caused by AGC and DRC.
Figure 2. Hardware enabled TPA2028D1 gain increment
It is worth noting that since it takes time to establish the internal state of the chip, it will produce a certain output delay. The delay of TPA2028 is about 6ms. Because this time is relatively short compared to the ramp-up time, and there is a certain delay when the processor plays the sudden sound, the output delay can be ignored in the general design. However, if there is a situation where the processor plays without delay in the actual application, it can be solved by adding a 6ms delay before the processor plays the burst file.
Figure 3. Output delay
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