This article introduces a new family of high-performance clock generators that offer the industry's most integrated clocking solution for 10/25/100G applications. Let's take a look at the related content with the analog electronic editor.
The new Si5332 clock family leverages Silicon Labs' proven MulTISynth fractional clock synthesis technology to provide a clocking solution with best-in-class frequency flexibility and 230fs rms jitter performance. A variety of Si5332 options covering 6, 8, and 12 clock outputs enable clock tree integration for demanding applications. These applications include very large data center switches, servers, storage, networking, small cellular networks, broadband, broadcast video, multifunction printers, and industrial applications.
Complex devices—such as Ethernet switches, high-speed switch fabrics, network processors, server SoCs, and FPGAs—integrate data path processing, CPU functions, and multiple serial/deserializers (SerDes) in a single IC. Therefore, these devices require a diverse combination of reference clocks. 10/25/100G SerDes have stringent jitter requirements and typically require a clock with a maximum jitter of 300fs rms. CPU phase-locked loops have lower jitter requirements, but spread-spectrum clocks are often used to minimize electromagnetic interference (EMI). Unlike traditional clocking solutions that use quartz oscillators, buffers, and fixed-frequency clock generators, the Si5332 clock generates all SerDes, processor, and system clocks in a single-chip device while providing significant jitter margin for system developers The clock tree can be simplified with confidence.
James Wilson, senior director of marketing for Silicon Labs' clock products, said: "Ultra-high-speed data centers are rapidly migrating from 10G to 25G, 50G and 100G Ethernet to accelerate data transmission and increase network efficiency. This new investment cycle is driving device manufacturers to switch Upgrade the port to a higher speed and use a higher performance clocking solution. By choosing Silicon Labs' Si5332 arbitrary frequency clock chip, system designers can optimize their clock tree design without compromising clock performance."
The Si5332 family offers a specially optimized reference clock for high-speed serial interconnects in next-generation data centers. The new family of products supports PCI Express, a long-standing mainstream standard for connecting microprocessors, networking, storage and memory. The PCI-SIG organization recently introduced PCI Express 4.0 (version 0.9), which supports 16 GT/s data rates. The Si5332 family is fully compliant with the PCI Express 4.0 standard while providing 60% of the jitter margin for the PCIe Gen 4 specification.
Other industry alliances, including CCIX, Gen-Z, NVLink, and OpenCAPI, are developing serial interconnect replacement technologies that support speeds up to 25 GT/s. In addition to requiring a low jitter clock, some of these solutions require a spread spectrum reference clock. The Si5332 family offers a versatile solution that supports dual independent spread-spectrum paths. Spread spectrum clock generation is enabled on a per-output basis, which enables a single clock device to support both mixed-spectrum and non-spread-frequency clock modes. All in all, these features make the Si5332 family the best solution for high-speed serial interconnect reference clocks.
The Si5332 clock generator is designed to simplify clock tree design without compromising performance or power consumption. The new family integrates two MulTISynth fractional clock synthesizers and five independent integer dividers, eliminating the need for fixed frequency clocks and oscillators to generate clocks. With 230fs rms jitter, the Si5332 clock offers 2-5 times better jitter performance than competing solutions while providing 10/25/100G SerDes clocking. The Si5332 clock integrates a large number of on-chip power regulators, eliminating the need for an off-chip expensive discrete low dropout (LDO) regulator that is typically required for competing solutions. The Si5332 family based on the MulTISynth architecture is also optimized for power efficiency and consumes 50-60% less power than competitors.
Each Si5332 clock output can be configured in LVPECL, LVDS, HCSL or LVCMOS clock formats and supports 1.8V-3.3V levels, which eliminates the need for discrete formats or voltage converters, simplifying interface design with FPGAs, ASICs and SoCs. In addition to I2C control, these clock products support user-defined control pins that do not require a serial interface and can be used to quickly configure each device. Like other Silicon Labs clock products, the Si5332 clock can be configured and customized using the flexible ClockBuilder Pro software.
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