In the MCU system, if the parallel port's I/O resources are insufficient, we can use the 74LS164 to expand the parallel I/O ports, thereby conserving the MCU’s I/O resources. The 74LS164 is a serial-in, parallel-out shift register with a clear terminal. This makes it an efficient way to manage limited I/O pins in microcontroller-based projects.
When using the MCU’s serial port for display purposes, it should operate in a transmission mode. The timing diagram illustrates how the serial port transmits 8-bit data from the lowest bit (D0) to the highest bit (D7) at a baud rate of Fosc/12. During this process, the RXD pin outputs the data sequentially. Once the entire byte is transmitted, the interrupt flag TI is set to "1", signaling the end of the transmission. It is crucial to note that the order of the bits matters significantly when interfacing the MCU’s serial port with the 74LS164. A mismatch in bit order can lead to incorrect data output.
Figure 2 shows the operation timing of the 74LS164, a serial-in, parallel-out shift register. When the enable B pin (pin 2) is low, the register is disabled and does not accept new data. When B is high, data can be input through pin A (pin 1). The first data bit is then shifted out through pin QH (pin 3), and after receiving all 8 bits, the first bit (D0) will appear at the QH output, while the last received bit (D7) will be at the QA terminal.
The hardware circuit shown in Figure 3 may cause issues due to the mismatch between the serial port’s bit order and the shift register’s output. Table 1 presents the segment code mapping, where segment a corresponds to D0 and segment h corresponds to D7. However, after the shift register receives the full byte, the QA output will actually reflect D7, not D0. This leads to a reversed segment order, causing incorrect display patterns. To fix this, the glyph code must be adjusted as shown in Table 2, ensuring that the correct segment codes are displayed on the corresponding pins.
In some cases, designers may prefer to use the original glyph codes from Table 1. In such scenarios, adjusting the connections between the display and the 74LS164 can achieve the correct output without modifying the code. The revised hardware setup is illustrated in Figure 4.
By analyzing the timing of the MCU’s serial port and the 74LS164, two effective software and hardware combinations were presented. These methods proved successful in a project involving an intelligent centrifugal switch speedometer, where the adjusted glyph codes matched the hardware configuration. Similar problems can arise when using other shift registers like the 74LS165, but the same timing-based approach applies.
The Proteus simulation diagram and accompanying code are provided for reference. The code includes functions for initializing the timer, handling interrupts, and sending data to the 74LS164. It also features a function to refresh the display buffer and another to update the digital tube display. The main loop continuously updates the display based on the time count, ensuring accurate representation of the data.
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